HDLC, High-level Data Link Control, is a popular ITU defined protocol used in data networking applications such as cellular base station switch controllers, frame relay switches, high bandwidth WAN links, xDSL and modern error correction. This protocol is responsible for transmitting data between network points. It organizes data into units, following the bit oriented packet transmission mode, and sends it across a network to a destination that verifies its successful arrival. The data stream and transmission rate is controlled from the network node (PCM highway clock) with a backpressure mechanism. This eliminates additional synchronization and buffering of the data at the network interface. Different variations of the protocol are used in different networks. For example, ISDN's D-channel uses a slightly modified version of HDLC
There are many types of HDLC and examples given in the following description are merely for clarifying reasons and in no way limit the invention to the examples.
HDLC uses the term “frame” to indicate an entity of data (or a protocol data unit) transmitted from one station to another. FIG. 1 is a graphical representation of a HDLC frame with an information field.
Every frame on the link must begin and end with a flag sequence field, F. Stations attached to the data link must continually listen for a flag sequence. The flag sequence can be an octet looking like 01111110. Flags are continuously transmitted on the link between frames to keep the link active. Two other bit sequences are used in HDLC as signals for the stations on the link. According to one exemplary embodiment, these two bit sequences are:                Seven 1's, but less than 15 signals an abort signal. The stations on the link know there is a problem on the link.        15 or more 1's indicate that the channel is in an idle state.        
The time between the transmissions of actual frames is called the interframe time fill. The interframe time fill is accomplished by transmitting continuous flags between frames. The flags may be in 8 bit multiples.
HDLC is a code-transparent protocol. It does not rely on a specific code for interpretation of line control. This means that a bit at position N in an octet has a specific meaning, regardless of the other bits in the same octet. If an octet has a bit sequence of 01111110, but is not a flag field, HDLC uses a technique called bit-stuffing to differentiate this bit sequence from a flag field. Once the transmitter detects that it is sending 5 consecutive 1's, in inserts a 0 bit to prevent a “phony” flag.
When the above sequence is transmitted, at the receiving end, the receiving station inspects the incoming frame. If it detects 5 consecutive 1's it looks at the next bit. If it is a 0, it pulls it out. If it is a 1, it looks at the 8th bit. If the 8th bit is a 1, it knows that an abort or idle signal has been sent. It then proceeds to inspect the following bits to determine appropriate action. HDLC achieves code-transparency in this manner. HDLC is not concerned with any specific bit code inside the data stream. It is only concerned with keeping flags unique.
Other fields comprise:
A: Address field
C: control field
I: Information field, and
CRC: Frame checking sequence.
The functionality of HDLC and its different fields are assumed to be known for skilled persons and not described herein in more detail.
During high loads on the bus, the routing function of the bus, i.e. the bus-master, will not function properly because its buffers become filled. Thus, the incoming traffic cannot be handled. To be able to stop the data from the slaves, i.e. the units transmitting data to the master, so that the buffers can be emptied a mechanism is needed.
It is possible to use a separate stop signal as the flow control, as illustrated in FIG. 2. FIG. 2 illustrates a simple data link comprising a number of Transmitters and a Receiver. The data flow is through an uplink bus. In case of an overflow state, the receiver signals the transmitters to stop sending data.
In JP 10013878, a stable communication processing at all times by limiting received calls from an ISDN line network depending on a data transmission quantity of a data input system is attained. A main CPU of a control unit monitors a data transmission quantity of a data highway based on a residual capacity of a dual port RAM, and a main CPU of an ISDN line interface unit monitors a data transmission quantity of the data highway 13 based on a residual capacity of a dual port RAM. When the data transmission quantity of the data highway exceeds a prescribed quantity, either or both the main CPU and the main CPU give an input reject request to a line internal bus interface/HDLC controller of the ISDN line interface unit to allow the controller to send the call reception reject request to an ISDN line network thereby limiting the arrival of succeeding data and preventing overload of reception data input system, resulting in conducting stable communication processing.
EP 647 082 concerns a data link controller (DLC), which employs buffers on both receiving and transmitting sides. These last-in, first-out buffers contain a position indicating that a character is the last one of a packet. In this way, a user need not monitor reception or transmission on a character-by-character basis, but need only concern themselves with packets. The receive and transmit FIFO's generate requests for more characters by monitoring the number of characters stored and thereby automatically receive and transmit characters without processor intervention. A four-stage mechanism permits monitoring of multiple contiguous frames (back-to-back frames) received. Control of the DLC is provided by status and control registers, which are accessible to the user via a microprocessor interface. Particular registers have bit positions monitoring status conditions in such a manner that the most-probable one of a set of conditions comprises the least-significant bit position, while the least-probable condition occupies the most-significant bit position. This affords simple shift and test technique for monitoring status conditions.
U.S. Pat. No. 5,878,279 relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.
In U.S. Pat. No. 5,410,542 a signal computing bus (SCbus) includes two bus structures: (a) a synchronous TDM data transport referred to as a data bus and (b) a serial message passing bus referred to as a message bus. The following three groups of functions are performed using the SCbus: (a) data transport over the data bus, (b) message passing over the message bus, and (c) data and message bus control. In a preferred embodiment, the data bus utilizes: 2 clocks, 1 frame pulse, 16 data busses, and 1 clock control (the clock control signal enables access to the bus and automatic switching from one clock master to another when an error is detected) and the message bus is fabricated using a master HDLC protocol with contention resolution.
EP 238 255 relates to an interface arrangement, which interconnects a business communication system with a telephone station set. All signaling from the business communication system is received by the personal computer, interpreted, and appropriate control signals are then forwarded under control of the software resident on the personal computer to activate the digital telephone station set. The signals from the digital telephone station set are intercepted by the personal computer, interpreted, modified and appropriate control messages and signaling are then forwarded by the personal computer to the business communication system. This arrangement enables a user to create software on the personal computer to control the operation of the telephone station set associated with the personal computer.
None of the cited documents use the technique of the invention, as described in the following, to achieve an optimal flow control based on present protocols.